1. Field of the Invention
The present invention relates to semiconductor memory devices having main word lines and sub word lines and adopting the split decoder system in which decoding of selectively activating the word lines to select memory cells is done in two steps and, more particularly, to a semiconductor memory device in which a memory cell array is divided into a plurality of blocks and sense amplifier columns are provided for individual blocks.
2. Description of the Background Art
Conventionally, methods for reducing the rise time constant of word lines include the metal piling method in which word lines are backed with first aluminum interconnection layers, as an example. However, pitches of the first aluminum wirings become narrower as the devices are miniaturized more, increasing the possibility of reduction of yield, and now moderating the pitches of word lines is important technique.
Now, the split decoder system described in the NEC Technical Journal Vol.47 No.3/1994, pp.69-73 is an example for realizing it, where the drivers of word lines are divided to make the rise time constant of word lines smaller.
In this system, sub word lines are selected by main word lines selectively activated by main row decoders (referred to as MRD, hereinafter) and decoded subdecode signals. For example, the main word lines are provided using first metal interconnections, signal lines for transmitting subdecode signals are provided using second metal interconnections, for example, and the sub word lines are provided using transistor gate interconnections. The sub word lines are connected to driving circuits for driving the sub word lines according to states of the main word lines and the subdecode signals. Separating into decoders for driving the main word lines and driving circuits for driving the sub word lines allows load distribution of word lines, which allows the word lines to rise at high speed. Furthermore, as compared with the metal piling method, pitches of the first metal interconnections can be larger as the number of ways of the subdecode signals increases. Now, the number of ways corresponds to the number of rows of a memory cell array allotted to all the sub word lines provided corresponding to one main word line.
In the dynamic random access memories (referred to as DRAM, hereinafter), since more electricity is consumed as the number of memory cells increases, a memory cell array may be divided into a plurality of blocks and sense amplifiers may be provided for each of the blocks so that the read operation can be effected only to a required block.
FIG. 16 and FIG. 17 show an example of possible configuration where the conventional split decoder system is applied to the conventional DRAM with its memory cell array divided into a plurality of blocks. FIG. 16 is a block diagram showing important parts of a DRAM with a memory cell array divided into a plurality of blocks. In the figure, BL.sub.1 -BL.sub.m denote blocks including a plurality of memory cells arranged in rows and columns and forming a memory cell array, MRD.sub.1 -MRD.sub.m denote main row decoders provided corresponding respectively to the blocks BL.sub.1 -BL.sub.m of the memory cell array, SA.sub.1 -SA.sub.m denote sense amplifier columns provided corresponding respectively to the blocks BL.sub.1 -BL.sub.m, Bu.sub.101 denotes a buffer for preventing undesirable electrical interaction between a circuit for generating a subdecode signal SDA.sub.1 and subdecode circuits, Bu.sub.102 denotes a buffer for preventing undesirable electrical interaction between a circuit generating a subdecode signal SDA.sub.1 , which is a complementary signal of the subdecode signal SDA.sub.1, and subdecode circuits, Bu.sub.103 denotes a buffer for preventing undesirable electric interaction between a circuit generating a subdecode signal SDA.sub.2 and subdecode circuits, Bu.sub.104 denotes a buffer for preventing undesirable electrical interaction between a circuit generating a subdecode signal SDA.sub.2 , which is a complementary signal of the subdecode signal SDA.sub.2, and subdecode circuits, 201-204 denote signal lines connected to outputs of the buffers Bu.sub.101 -Bu.sub.104 and provided on the memory cell array to transmit the subdecode signals, 101 denotes a subdecode band formed of a plurality of subdecode circuits provided in an odd column of the block BL.sub.1, 102 denotes a subdecode band formed of a plurality of subdecode circuits provided in an even column of the block BL.sub.1, 111 denotes a subdecode band formed of a plurality of subdecode circuits provided in an odd column in the block BL.sub.2, and 112 denotes a subdecode band formed of a plurality of subdecode circuits provided in an even column in the block BL.sub.2.
The plurality of blocks BL.sub.1 -BL.sub.m are provided with a plurality of columns of subdecode bands, where the subdecode bands of odd columns of each block BL.sub.1 -BL.sub.m are supplied with the subdecode signals, SDA.sub.1, SDA.sub.1 through the plurality of sets of buffers Bu.sub.101, Bu.sub.102, and the subdecode bands of even columns are provided with the subdecode signals SDA.sub.2, SDA.sub.2 through the plurality of sets of buffers Bu.sub.103, Bu.sub.104. Accordingly, the subdecode bands of the same column in the respective blocks BL.sub.1 -BL.sub.m are simultaneously supplied with the same subdecode signals irrespective of a state of that block, a selected state or an unselected state.
FIG. 17 is a block diagram showing arrangement of the subdecode circuits in one of the plurality of blocks shown in FIG. 16. In FIG. 17, MWL.sub.1 -MWL.sub.m denote the first through m-th main word lines, SWL.sub.1a -SWL.sub.1b denote sub word lines connected to some of the plurality of memory cells in the first row in the block BL.sub.1, SWL.sub.2a -SWL.sub.2b denote sub word lines connected to some of the plurality of memory cells in the second row in the block BL.sub.1, D101 denotes a subdecode circuit connected to the main word line MWL.sub.1 and the sub word line SWL.sub.1a and belonging to the subdecode band of the first column in the block BL.sub.1, D102 denotes a subdecode circuit connected to the main word line MWL.sub.1 and the sub word line SWL.sub.2a and belonging to the subdecode band of the second column in the block BL.sub.1, D103 denotes a subdecode circuit connected to the main word line MWL.sub.1 and the sub word line SWL.sub.1b and belonging to the subdecode band of the third column in the block BL.sub.1, D104 denotes a subdecode circuit connected to the main word line MWL.sub.2 and a sub word line corresponding to some of the memory cells in the third row in the block BL.sub.1 and belonging to the subdecode band of the first column in the block BL.sub.1, and the same reference characters as those in FIG. 16 denote the same parts as those designated by the same reference characters in FIG. 16.
Increasing the number of columns of the subdecode bands can shorten the length of a sub word line and reduce the number of memory cells for one subdecode circuit, but, on the other hand, it is disadvantageous in that the number of subdecode circuits increases to increase power consumption and the area for placement of the subdecode circuits.
The main word lines MWL.sub.1 -MWL.sub.m are disposed parallel to the sub word lines, that is, the transfer gates in the memory cells and the sub word lines are divided into n-1 relative to the main word line length in the main word line direction. The subdecode bands 101-104 are disposed in the boundaries of the division. On this subdecode band, signal lines 201-204 etc. for transmitting the subdecode signals SDA.sub.1, SDA.sub.1 , SDA.sub.2, and SDA.sub.2 are provided perpendicular to the main word lines MWL.sub.1 -MWL.sub.m. The subdecode circuits (referred to as SRD, hereinafter) are disposed at intersections of the main word lines and the subdecode signals. Detailed structure of the SRD is shown in FIG. 18. In FIG. 18, Q1 denotes a P-channel MOS transistor having one of its current electrodes supplied with the subdecode signal SDS and its other current electrode connected to the sub word line SWL and its control electrode connected to the main word line, Q2 denotes an N-channel MOS transistor having one of its current electrodes connected to the sub word line SWL, its control electrode connected to the main word line MWL and its other current electrode grounded, and Q3 denotes an N-channel MOS transistor having one of its current electrodes connected to the sub word line SWL, its control electrode supplied with the subdecode signal SDS and its other current electrode grounded. Operation of the subdecode circuit is shown in Table 1. In Table 1, V.sub.PP is a voltage higher than the voltage V.sub.CC, and gnd is a ground voltage.
TABLE 1 ______________________________________ Selected Block MWL Active Portion MWL Inactive Portion Sub- decode Subdecode Subdecode Subdecode Stand- Circuit Circuit Circuit Circuit by Active Inactive Active Inactive ______________________________________ MWL V.sub.PP gnd gnd V.sub.PP V.sub.PP SDS gnd V.sub.PP gnd V.sub.PP gnd SDS V.sub.CC gnd V.sub.CC gnd V.sub.CC ______________________________________
The main word line MWL is supplied with the voltage gnd when activated and the voltage V.sub.PP when deactivated. When activated, the voltage V.sub.PP is provided as the subdecode signal SDS and the voltage gnd is provided as the subdecode signal SDS, and when deactivated, the voltage gnd is provided as the subdecode signal SDS and the voltage V.sub.CC is provided as the subdecode signal SDS. Accordingly, in standby, the main word line MWL is supplied with the voltage V.sub.PP, the signal line is supplied with the voltage gnd as the subdecode signal SDS, and the signal line is supplied with the voltage V.sub.CC as the subdecode signal SDS.
When the main word line MWL is activated, the ground voltage gnd is provided to the main word line, and the voltage V.sub.PP is provided as the subdecode signal SDS to one of the current electrodes of the transistor Q1 so as to activate the sub word line. Thus, the transistor Q1 attains an ON state and provides the voltage V.sub.PP to the sub word line SWL. Since the high voltage V.sub.PP is provided as the subdecode signal SDS when active, the power consumption of the buffer Bu.sub.101, or the buffer Bu.sub.103 outputting the subdecode signal SDS becomes larger as compared with the buffer Bu.sub.102 or Bu.sub.104 which outputs the voltage V.sub.CC, as the subdecode signal SDS when it is inactive.
The voltage V.sub.PP must be applied to the main word line MWL in standby, but the action of decreasing the level of the voltage V.sub.PP caused by the leakage current from the main word line MWL becomes large, since a large number of main word lines MWL are provided in the memory cell array. Generally, the voltage V.sub.PP is obtained by raising the voltage V.sub.CC. In such a case, a circuit which generates the voltage V.sub.PP operates to hold the level of the voltage V.sub.PP and increases the standby current. Also, after the standby state is held in a long time, and before the circuit generating the voltage V.sub.PP operates to supply the voltage V.sub.PP again, that is, when the subdecode signals SDS, SDS are activated with the voltage V.sub.PP having its level decreased, malfunction may occur.
In FIG. 16, the subdecode structure of the alternate arrangement type of two-way is shown to simplify the description. In this case, the two sub word lines SWL.sub.1a, SWL.sub.2a are provided for the single main word line MWL.sub.1, for example. Pitch of the single main word line formed of the first metal interconnection on the two sub word lines formed of gate polysilicon can be reduced to 1/2 in comparison with the metal piling method. As the subdecode signals are arranged in the alternate arrangement manner, subdecode circuits receiving the same subdecode signals only can be arranged for a single column of subdecode band.
In the DRAM as described above which is structured by combining conventional arts, all of the divided sub word lines for one column with respect to the main word line direction must be activated at the time when the signal on the main word line rises, for addresses are inputted by the time-division system. Hence, all the subdecode signals and subdecode circuits operate. Accordingly, there is a problem that the charge/discharge current of the subdecode signals and subdecode circuits increases to increase the power consumption as the sub word lines are divided into a larger number.
Furthermore, there is also a problem that the leakage current from the main word line increases when standby, increasing the power consumption.